The invention is generally related to the field of MOSFET transistor fabrication and more specifically to a novel process for fabricating a high performance MOSFET.
As MOSFET technology continues to scale further into the sub-micron region, it becomes increasingly difficult to keep sufficiently low gate sheet resistance, low junction capacitance, and low junction depth of source/drain extensions under the gate. As transistors are scaled into the deep sub-micron region, the polysilicon gate linewidths become narrower and narrower. This increases the gate sheet resistance. Achieving low gate sheet resistance becomes difficult even when silicided polysilicon is used. In addition it becomes increasingly difficult to form the sub-micron polysilicon lines using currently available optical photolithographic techniques. For polysilicon linewidths in the sub-micron regime optical proximity correction is used during polysilicon gate formation. Optical proximity correction adds cost and complexity to the MOSFET fabrication process.
The source/drain junction regions and source/drain extensions must also become shallower to avoid undesired short-channel effects and roll-off of the threshold voltage at short channel lengths. However, in the deep sub-micron region, it is difficult to achieve shallower doping profiles because in conventional processes the source and drain extension implants are subjected to the high temperature source/drain implant anneal which causes diffusion of the implanted species. Therefore, there is a need for a MOSFET transistor structure that can be scaled into the sub-micron region while maintaining sufficiently low gate sheet resistance, shallow junction depth, and low junction capacitance.
One of the most challenging issues facing the fabrication of sub-micron transistors is forming shallow source/drain extensions under the sidewall spacer. This problem is especially severe for the replacement gate transistor design if inner sidewalls spacers are added to decrease the linewidth of the replacement gate which is formed in the slot in an insulator left by removal of the disposable gate. There are a number of prior art inventions in which a gate is formed in a slot in an insulator by a means other than the removal of the disposable gate. A common problem with these inventions is how to place a shallow drain extender underneath sidewall spacers deposited in the slot. In one prior art example, after nitride spacers are formed on the inner walls of the slot, thermal oxide is grown in the space between the sidewalls. Next, the nitride spacers are removed and the shallow source/drain junction extenders are implanted into the spaces where the nitride spacers have been removed with the thermal oxide in the center blocking these implants. Next, the nitride spacers are reformed, the center thermal oxide removed, and replaced with a thin gate oxide. Finally, the slot is filled with the gate material. This is a very complicated process which is not very manufacturable.
The instant invention is an inverted MOSFET process. This process comprises the steps of: providing a semiconductor substrate containing isolation structures; forming a gate-like structure over said semiconductor substrate; forming transistor source and drain regions in said semiconductor substrate adjacent to said gate-like structure; forming a first dielectric film over said semiconductor substrate wherein said first dielectric film is adjacent to said gate-like structure; removing said gate-like structure; forming removable sidewall structures adjacent to said first dielectric film in a region from which said gate-like structure was removed; forming a gate dielectric on said semiconductor substrate between said removable sidewall structures; forming a replacement gate adjacent to said removable sidewall structures over said gate dielectric; removing said removable sidewall structures; and forming pocket regions and drain/source extension regions in said semiconductor substrate adjacent to said replacement gate.
The inverted MOSFET process offers a number of advantages over conventional MOSFET processes. The inverted process results in spot implants, a flared gate shape, low temperature anneals for the drain and source extension implants, a larger minimum feature (i.e. etched gate size which allows less optical proximity correction during lithography). These characteristics results in higher drive currents form the transistors. This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.